Object Counter
Components Used
Sr.
No.
|
Components
required
|
Quantity
|
1
|
Resistor-1KΩ
|
5
|
2
|
Resistor-10KΩ
|
1
|
3
|
Resistor-47KΩ
|
1
|
4
|
Resistor-20
Ω
|
1
|
5
|
Resistor-200
Ω
|
2
|
6
|
Variable
Resistor-500 Ω
|
1
|
7
|
Capacitor-
1µf
|
1
|
8
|
Capacitor-
0.1µf
|
1
|
9
|
Capacitor-
100nf
|
12
|
10
|
Push
Button
|
2
|
11
|
LED
|
1
|
12
|
LDR
|
1
|
13
|
Transistor
BC547
|
1
|
14
|
IC
74LS390-Dual 4-Bit Decade Counter
|
2
|
15
|
IC
74LS48-BCD to 7-Segment Decoder
|
4
|
16
|
IC
5082-7 Segment Display
|
4
|
17
|
IC
555 Timer
|
1
|
18
|
IC
54LS00-Quad 2 i/p NAND Gates
|
1
|
19
|
IC
74LS74A-Dual positive edge triggered D-Flip Flop
|
1
|
20
|
IC
74LS04- Hex Inverter
|
1
|
Introduction
In digital logic and computing, a counter is a device which
stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal.
Electronic Counters:
In electronics, counters can be implemented quite
easily using register-type circuits such as the flip-flop, and a wide variety
of classifications exist:
•
Asynchronous (ripple)
counter:
Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop.
Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop.
Asynchronous counters are also
called ripple-counters because of the way the clock pulse ripples it way
through the flip-flops.
•
Synchronous counter:
All state bits change under control of a single clock. All flip-flops are clocked simultaneously by an external clock.
All state bits change under control of a single clock. All flip-flops are clocked simultaneously by an external clock.
Synchronous counters are faster
than asynchronous counters because of the simultaneous clocking.
•
Decade counter:
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each digit binary encoded (that is, it may count in binary-coded decimal. The decade counter is also known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9).
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each digit binary encoded (that is, it may count in binary-coded decimal. The decade counter is also known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9).
•
Up/down counter:
A counter that can change state in either direction, under the control of an up or down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.
A counter that can change state in either direction, under the control of an up or down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.
•
Ring counter:
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states.A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used. It can be used as a cycle counter of n states.
A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states.A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used. It can be used as a cycle counter of n states.
•
Johnson counter (a twisted ring counter):
A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage. These counters find specialist applications, including those similar to the decade counter, digital-to-analog conversion, etc. They can be implemented easily using D- or JK-type flip-flops.
A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage. These counters find specialist applications, including those similar to the decade counter, digital-to-analog conversion, etc. They can be implemented easily using D- or JK-type flip-flops.
The connection of the pins for a DIP package is as follows:
Pin
|
Name
|
Purpose
|
1
|
GND
|
Ground reference voltage, low level (0 V)
|
2
|
TRIG
|
The OUT pin goes high and a timing interval starts when this input
falls below 1/2 of CTRL voltage (which is typically 1/3 of VCC,
when CTRL is open).
|
3
|
OUT
|
|
4
|
RESET
|
A timing interval may be reset by driving this input to GND, but the
timing does not begin again until RESET rises above approximately 0.7 volts.
Overrides TRIG which overrides THR.
|
5
|
CTRL
|
Provides "control" access to the internal voltage divider
(by default, 2/3 VCC).
|
6
|
THR
|
The timing (OUT high) interval ends when the voltage at THR is
greater than that at CTRL (2/3 VCC if CTRL is open).
|
7
|
DIS
|
|
8
|
VCC
|
Positive supply voltage, which is usually between 3 and 15 V
depending on the variation.
|
Pin 5 is
also sometimes called the CONTROL VOLTAGE pin. By applying a voltage to the
CONTROL VOLTAGE input one can alter the timing characteristics of the device.
In most applications, the CONTROL VOLTAGE input is not used. It is usual to
connect a 10 nF capacitor between pin 5 and 0 V to prevent interference. The
CONTROL VOLTAGE input can be used to build an astable with a frequency
modulated output.
Modes
The 555 has three operating modes:
•
Monostable mode: In this mode, the 555 functions as a
"one-shot" pulse generator. Applications include timers, missing
pulse detection, bounce free switches, touch switches, frequency divider,
capacitance measurement, pulse-width modulation (PWM) and so on.
•
Astable (free-running) mode : The 555 can operate as an oscillator. Uses include LED and lamp flashers, pulse generation, logic clocks, tone
generation, security alarms, pulse position modulation and so on.
Bistable mode or Schmitt trigger: The 555 can operate as a flip-flop, if the DIS pin is not connected and no
capacitor is used. Uses include bounce-free latched switches.
Monostable mode:
In the monostable mode, the 555 timer acts as a "one-shot"
pulse generator. The pulse begins when the 555 timer receives a signal at the
trigger input that falls below one third of the voltage supply. The width of
the output pulse is determined by the time constant of an RC network, which
consists of a capacitor (C)
and a resistor (R).
The output pulse ends when the voltage on the capacitor equals 2/3 of the
supply voltage. The output pulse width can be lengthened or shortened to the
need of the specific application by adjusting the values of R and C.
The output pulse width of time t, which is the time it takes to
charge C to 2/3 of the supply voltage, is given by
While using the timer IC in monostable mode, the main disadvantage is
that the time span between any two triggering pulses must be greater than the
RC time constant.
Bistable mode:
In bistable mode, the 555 timer acts as a basic flip-flop. The trigger
and reset inputs (pins 2 and 4 respectively on a 555) are held high via Pull-up resistors while the threshold input (pin 6) is simply grounded. Thus
configured, pulling the trigger momentarily to ground acts as a 'set' and
transitions the output pin (pin 3) to Vcc (high state). Pulling the reset input
to ground acts as a 'reset' and transitions the output pin to ground (low
state). No capacitors are required in a bistable configuration. Pin 5 (control)
is connected to ground via a small-value capacitor (usually 0.01 to 0.1 µF);
pin 7 (discharge) is left floating.
Astable mode:
In astable mode, the 555
timer puts out a continuous stream of rectangular pulses having a specified
frequency. Resistor R1 is connected between VCC and
the discharge pin (pin 7) and another resistor (R2) is connected
between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin
6) pins that share a common node. Hence the capacitor is charged through R1 and
R2, and discharged only through R2, since pin 7 has low
impedance to ground during output low intervals of the cycle, therefore discharging
the capacitor.
In the astable mode, the frequency of the pulse stream depends on the
values of R1, R2 and C:
Dual 4 Bit Decade Counter (DM74LS390)
General Description:
Each of these monolithic circuits contains
eight masterslave flip-flops and additional gating to implement two individual
four-bit counters in a single package. The DM74LS390 incorporates dual
divide-by-two and divide by-five counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to
divide-by-100. When connected as a bi-quinary counter, the separate
divide-by-two circuit can be used to provide symmetry (a square wave) at the
final output stage. The DM74LS390 has parallel outputs from each counter stage so
that any sub multiple of the input count frequency is available for
system-timing signals.
Features:
■Dual version of the popular DM74LS90
■DM74LS390...individual clocks for A and B
flip-flops provide dual ÷ 2 and ÷ 5 counters
■Direct clear for each 4-bit counter
■Typical maximum count frequency...35 MHz
Pins:
Truth table:
Bcd to 7- Segment Decoder
The IC 74LS48 is a BCD to 7-Segment Decoder consisting of NAND
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates
and one driver are connected in pairs to make BCD data and its
complement
available to the seven decoding AND-OR-INVERT gates. The remaining
NAND gate and three input buffers provide lamp test, blanking
input/rippleblanking input for the LS48.
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive other
components.
The relative positive logic output levels, as well as conditions
required at the
auxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and/or trailing edge
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated
any
time when the BI/RBO node is HIGH. Both devices contain an overriding
blanking input (BI) which can be used to control the lamp intensity by
varying
the frequency and duty cycle of the BI input signal or to inhibit the
outputs.
Top view:
Truth table:
7-Segment Display
A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display
device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying
numerical information.
Concept and visual structure
The seven elements of the display can be lit in different combinations
to represent the arabic numerals. Often the seven segments are arranged in
an oblique (slanted) arrangement, which aids readability. In most
applications, the seven segments are of nearly uniform shape and size (usually
elongated hexagons, though trapezoids and rectangles can also be used), though in the case of adding machines, the vertical segments are longer and more oddly shaped at the ends in
an effort to further enhance readability.
The seven segments are arranged as a rectangle of two vertical segments on each side with one horizontal segment
on the top, middle, and bottom. Additionally, the seventh segment bisects the
rectangle horizontally. There are also fourteen-segment
displaysand sixteen-segment
displays (for
full alphanumeric); however, these have mostly been replaced by dot-matrix displays.
The segments of a 7-segment display are referred to by the letters A to
G, where the optional DP decimal point (an "eighth segment") is used for the display ofnon-integer
numbers.
Implementations
Seven-segment displays may
use a liquid crystal display (LCD), a light-emitting diode (LED) for each segment, or other light-generating or
controlling techniques such as cold cathode gas discharge, vacuum fluorescent, incandescent
filaments,
and others.
There are two types of LED 7-segment displays:
•
common cathode (CC)
•
common anode (CA)
The common anode has all the anodes of the 7-segments connected
together. Shown below is a common anode seven segment.
A common cathode seven segment is different from a common anode
segment in that the cathodes of all the LEDs are connected together. For the
use of this seven segment the common cathode connection must be grounded and
power must be applied to appropriate segment in order to illuminate that
segment.
DM74LS74A
Dual Positive -Edge -Triggered D Flip-Flops
General
Description:
This device
contains two independent positive-edge-triggered D flip-flops with complementary
outputs. The information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering occurs at a
voltage level
and is not directly related to the transition time of the rising edge of the
clock. The data on the D input may be changed while the clock is LOW or HIGH
without affecting the outputs as long as the data setup and hold times are not
violated. A low logic level on the preset or clear inputs will set or reset the
outputs regardless of the logic levels of the other inputs.
Connection
Diagram:
Function Table:
DM74LS00
Quad 2- Input Nand Gates
General
Description:
This device
contains four independent gates each of which performs the logic NAND function.
PIN Diagram:
Function Table:
Working of the Circuit
Depending upon
•
555 multivibrator in astable mode
•
Two dual 4 bit decade counter
•
Four BCD to Seven Segment Decoder
•
Four 7-Segment Display
The 555 timer
puts out a continuous stream of rectangular pulses having a specified frequency
of 500 Hz.
The clock pulse of 555 multivibrator is then provided
to the IC 74LS390. This IC is a dual
4-bit decade counter divided into four separately clocked sections. The counter
IC has two set of divide -by- two section and divide- by- five section. The
pulse is given to pin 1 of the IC 74LS390 and the output is taken from pin 3
which gets divided by 2 and this output is taken as the input at pin 4 giving
three outputs at pin 5,6,7 and the output at pin 7 gets divided by 5 and this
acts as input at pin 15 and we get the output at pin 13 which is again divided
by 2 and this output is taken as the
input at pin 12 giving three outputs at pin 11,10,9 and the output at pin 9 and
gets divided again by 5. And in total the final output’s frequency gets divided
by 100.This output is given to the second IC 74LS390 and it works in the same
way as explained above. Hence we get the output at 50mHz.
The pulse is applied to the IC74LS48 BCD to seven segment decoder implemented
as a two-level AND-OR circuit. It converts a 4-bit binary-coded decimal value
that is the numbers 0 to 9 coded as 0000 to 1001, into the code required to
drive a seven-segment display IC5082
The input a four-bit BCD (Binary-Coded Decimal)
value, and energize the proper output lines to form the corresponding decimal
digit on the 7-segment LED display. The BCD inputs are designated A, B, C, and
D in order from least-significant to most-significant. Outputs are labeled a,
b, c, d, e, f, and g, each letter corresponding to a standardized
segment designation for 7-segment displays.
A reset circuit
is also used to reset the count to zero. For this a push button is used whose
one end is connected to +5V supply and another end is grounded through a
resistance of a 10K. The output of this push button is connected to pin 2 &
14 of IC 74LS390. This output is also connected to the clear pin of D Flip-Flop
through a Hex inverter.
To provide the Start pulse for the counter another circuit is made
using IC 74LS74A. It has dual positive-edge-triggered D flip-flops. The clock input
is provided to pin 3 of this IC through a resistance of 1K connected to one end
of a push-button which is also grounded. The other end of this push button is
connected to a supply of +5V. The data input to pin 2 is connected to +5V
supply through a resistance of 1K and it is also connected to the preset at pin
4. The output of this at pin 5 is then provided to pin 12 of IC 74LS00.The
final output pulse at pin 11 of IC 74LS00 is connected to pin 1 of IC 74LS390.
When the reset button is pressed a high pulse is generated which is
then passed through an inverter to give a low pulse. This low pulse is provided
to the clear pin of D-Flip Flop. Due to this the output of flip flop is low and
no output pulse is provided to counter circuit and the circuit is reset to
zero.
Now, when start button is pressed, a low to high pulse is generated which
provides a clock input to the flip flop and thus the high pulse at input D is
provided at the output. This high pulse is connected to the counter IC. Thus
the counter circuit starts operating.
Working:
The LED is used
to emit light which is then directed on the LDR. Depending on
the intensity
of light, the resistance of the LDR
changes. When the light is OFF the minimum resistance of LDR is 15K and in
presence of light the maximum resistance is 6K. The output of LDR is connected to
the base of transistor BC547.
When light falls
on the LDR, its resistance is low, the total base voltage of BC547 is approx. 0.56
volt which is less than 0.7 volt. This voltage is less than that required for
the transistor to conduct and it goes in cut-off region. Thus it doesn’t
conduct and we get high output.
Now, when any
object is placed between the LED and LDR, the light falling on the LDR is
interrupted and its resistance increases. The base voltage of BC547 becomes
approx. 1.1 volt which is enough for the transistor to operate in saturation
region. Thus it conducts and provides alow (0 volt)output and when object is
passed and light is sensed by LDR, we get high output at collector .In this way
we get triggerpulse for the monoshot circuit.
The IC 54LS00 is
used in monostable multivibrator configuration. Initially, pin 1 and 2 is grounded through R hence output at pin 3 is
high and pin 9 is also high. The collector output of the transistor
provides an input pulse to the pin 10. These conditions make pin 8, low and at pin 6 we get low output. This
output is then provided to pin 13 of the same IC. The final output of this IC
at pin 11 is provided to decade counter for counting.
The counter circuit thus counts the no. of
times any object is passed between the LED and LDR. This circuit can count upto
a maximum value of 9999.
Research by:
Pooja Bhati & Shivkant Paswan
